The present invention is directed, in general, to microprocessors and, more particularly, to a processor architecture employing a pipelined, superscalar floating point unit (FPU) that is capable of executing floating point instructions out of order.
The ever-growing requirement for high performance computers demands that computer hardware architectures maximize software performance. Conventional computer architectures are made up of three primary components: (1) a processor, (2) a system memory and (3) one or more input/output devices. The processor controls the system memory and the input/output (xe2x80x9cI/Oxe2x80x9d) devices. The system memory stores not only data, but also instructions that the processor is capable of retrieving and executing to cause the computer to perform one or more desired processes or functions. The I/O devices are operative to interact with a user through a graphical user interface (xe2x80x9cGUIxe2x80x9d) (such as provided by Microsoft Windows(trademark) or IBM OS/2(trademark)), a network portal device, a printer, a mouse or other conventional device for facilitating interaction between the user and the computer.
Over the years, the quest for ever-increasing processing speeds has followed different directions. One approach to improve computer performance is to increase the rate of the clock that drives the processor. As the clock rate increases, however, the processor""s power consumption and temperature also increase. Increased power consumption is expensive and high circuit temperatures may damage the processor. Further, the processor clock rate may not increase beyond a threshold physical speed at which signals may traverse the processor. Simply stated, there is a practical maximum to the clock rate that is acceptable to conventional processors.
An alternate approach to improve computer performance is to increase the number of instructions executed per clock cycle by the processor (xe2x80x9cprocessor throughputxe2x80x9d). One technique for increasing processor throughput is pipelining, which calls for the processor to be divided into separate processing stages (collectively termed a xe2x80x9cpipelinexe2x80x9d). Instructions are processed in an xe2x80x9cassembly linexe2x80x9d fashion in the processing stages. Each processing stage is optimized to perform a particular processing function, thereby causing the processor as a whole to become faster.
xe2x80x9cSuperpipeliningxe2x80x9d extends the pipelining concept further by allowing the simultaneous processing of multiple instructions in the pipeline. Consider, as an example, a processor in which each instruction executes in six stages, each stage requiring a single clock cycle to perform its function. Six separate instructions can therefore be processed concurrently in the pipeline; i.e., the processing of one instruction is completed during each clock cycle. The instruction throughput of an n-stage pipelined architecture is therefore, in theory, n times greater than the throughput of a non-pipelined architecture capable of completing only one instruction every n clock cycles.
Another technique for increasing overall processor speed is xe2x80x9csuperscalarxe2x80x9d processing. Superscalar processing calls for multiple instructions to be processed per clock cycle. Assuming that instructions are independent of one another (the execution of each instruction does not depend upon the execution of any other instruction), processor throughput is increased in proportion to the number of instructions processed per clock cycle (xe2x80x9cdegree of scalabilityxe2x80x9d). If, for example, a particular processor architecture is superscalar to degree three (i.e., three instructions are processed during each clock cycle), the instruction throughput of the processor is theoretically tripled.
These techniques are not mutually exclusive; processors may be both superpipelined and superscalar. However, operation of such processors in practice is often far from ideal, as instructions tend to depend upon one another and are also often not executed efficiently within the pipeline stages. In actual operation, instructions often require varying amounts of processor resources, creating interruptions (xe2x80x9cbubblesxe2x80x9d or xe2x80x9cstallsxe2x80x9d) in the flow of instructions through the pipeline. Consequently, while superpipelining and superscalar techniques do increase throughput, the actual throughput of the processor ultimately depends upon the particular instructions processed during a given period of time and the particular implementation of the processor""s architecture.
The speed at which a processor can perform a desired task is also a function of the number of instructions required to code the task. A processor may require one or many clock cycles to execute a particular instruction. Thus, in order to enhance the speed at which a processor can perform a desired task, both the number of instructions used to code the task as well as the number of clock cycles required to execute each instruction should be minimized.
Statistically, certain instructions are executed more frequently than others. If the design of a processor is optimized to rapidly process the instructions which occur most frequently, then the overall throughput of the processor can be increased. Unfortunately, the optimization of a processor for certain frequent instructions is usually obtained only at the expense of other less frequent instructions, or requires additional circuitry, which increases the size of the processor.
What is needed in the art is a more efficient way to execute instructions in a processor and, more specifically, a faster way of executing floating point instructions in a processor.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a more efficient FPU architecture. In the attainment of the above primary object, the present invention provides, for use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, an FPU for receiving decoded ones of the floating point instructions and a method of processing the decoded ones of the floating point instructions. In one embodiment, the FPU includes: (1) a second number of floating point pipelines that execute the floating point instructions, the second number being at least one and less than the first number, the floating point pipeline having a load unit, an execution core and a store unit, (2) a floating point checkpoint buffer, coupled to the decode units, that queues the decoded ones of the floating point instructions for allocation to the floating point pipelines and (3) a floating point register file, coupled to and cooperable with the floating point checkpoint buffer, that preserves states of the execution core to allow the floating point pipelines to execute the floating point instructions out of order.
The present invention therefore introduces a novel FPU architecture in which floating point instructions received from a larger number of decode units can be appropriately buffered and checkpointed to allow out-of-order execution thereof in a smaller number of floating point pipelines. The first number can be two or more and the second number can be one or more, provided that the second number always remain less than the first number.
In one embodiment of the present invention, the FPU further includes reservation stations, coupled to the floating point checkpoint buffer and corresponding to each of the floating point pipelines, that controls the allocation of the floating point instructions. In an FPU having at least two floating point pipelines, the reservation stations are therefore distributed between or among the pipelines.
In one embodiment of the present invention, the first number is three, the second number is two and the floating point register file comprises a floating point physical register file and a floating point logical register file. The structure and operation of the register file(s) will be set forth in the Detailed Description to follow.
In one embodiment of the present invention, the second number is two, the FPU comprising a first floating point pipeline having a floating point adder unit and a second floating point pipeline having a floating point multiplier unit, the FPU being asymmetric. Of course, the present invention is fully operable with symmetric pipelines.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.